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Tytuł pozycji:

A III-V nanowire channel on silicon for high-performance vertical transistors.

Tytuł:
A III-V nanowire channel on silicon for high-performance vertical transistors.
Autorzy:
Tomioka K; Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-8628, Japan. />Yoshimura M
Fukui T
Źródło:
Nature [Nature] 2012 Aug 09; Vol. 488 (7410), pp. 189-92.
Typ publikacji:
Journal Article; Research Support, Non-U.S. Gov't
Język:
English
Imprint Name(s):
Publication: Basingstoke : Nature Publishing Group
Original Publication: London, Macmillan Journals ltd.
References:
Nature. 2011 Nov 16;479(7373):310-6. (PMID: 22094690)
Ultramicroscopy. 2007 Nov;107(12):1186-93. (PMID: 17391848)
Nano Lett. 2008 Oct;8(10):3475-80. (PMID: 18783279)
Nature. 2011 Nov 16;479(7373):317-23. (PMID: 22094691)
Nature. 2011 Nov 16;479(7373):329-37. (PMID: 22094693)
Nanotechnology. 2009 Apr 8;20(14):145302. (PMID: 19420521)
Nanotechnology. 2012 Jan 13;23(1):015302. (PMID: 22155896)
Entry Date(s):
Date Created: 20120803 Date Completed: 20120913 Latest Revision: 20211021
Update Code:
20240104
DOI:
10.1038/nature11293
PMID:
22854778
Czasopismo naukowe
Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

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