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Tytuł:
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Minimizing Global Buffer Access in a Deep Learning Accelerator Using a Local Register File with a Rearranged Computational Sequence.
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Autorzy:
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Lee M; Department of Electronic Engineering, Hanyang University, Seoul 04763, Korea.
Zhang Z; Department of Electronic Engineering, Hanyang University, Seoul 04763, Korea.
Choi S; Department of Electronic Engineering, Hanyang University, Seoul 04763, Korea.
Choi J; Department of Electronic Engineering, Hanyang University, Seoul 04763, Korea.
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Źródło:
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Sensors (Basel, Switzerland) [Sensors (Basel)] 2022 Apr 18; Vol. 22 (8). Date of Electronic Publication: 2022 Apr 18.
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Typ publikacji:
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Journal Article
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Język:
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English
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Imprint Name(s):
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Original Publication: Basel, Switzerland : MDPI, c2000-
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MeSH Terms:
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Deep Learning*
Records
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Grant Information:
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2020-0-01297 Institute of Information & Communications Technology Planning & Evaluation(IITP) grant funded by the Korea government (MSIT)
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Contributed Indexing:
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Keywords: deep learning accelerator; field-programmable gate array (FPGA); local register file; rearrangement of computational sequence
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Entry Date(s):
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Date Created: 20220423 Date Completed: 20220426 Latest Revision: 20220429
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Update Code:
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20240105
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PubMed Central ID:
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PMC9032599
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DOI:
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10.3390/s22083095
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PMID:
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35459079
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We propose a method for minimizing global buffer access within a deep learning accelerator for convolution operations by maximizing the data reuse through a local register file, thereby substituting the local register file access for the power-hungry global buffer access. To fully exploit the merits of data reuse, this study proposes a rearrangement of the computational sequence in a deep learning accelerator. Once input data are read from the global buffer, repeatedly reading the same data is performed only through the local register file, saving significant power consumption. Furthermore, different from prior works that equip local register files in each computation unit, the proposed method enables sharing a local register file along the column of the 2D computation array, saving resources and controlling overhead. The proposed accelerator is implemented on an off-the-shelf field-programmable gate array to verify the functionality and resource utilization. Then, the performance improvement of the proposed method is demonstrated relative to popular deep learning accelerators. Our evaluation indicates that the proposed deep learning accelerator reduces the number of global-buffer accesses to nearly 86.8%, consequently saving up to 72.3% of the power consumption for the input data memory access with a minor increase in resource usage compared to a conventional deep learning accelerator.