Scaling to the End of Silicon with EDGE Architectures. (cover story)

The TRIPS architecture is the first instantiation of an Explicit Data Graph Execution (EDGE) instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance. Instruction set architectures have long lifetimes because introducing a new industry standard architecture (ISA) is tremendously disruptive to all aspects of a computer system. This article will discuss a) the need for companies to introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible, and b) the development of a new class of ISAs, called EDGE, that will match the characteristics of semiconductor technology over the next decade. Moreover, the rest of the article will elucidate the following: a) TRIPS prototype microarchitecture; b) TRIPS code example; c) EDGE optimization in the Scale compiler; d) main parallelism classes supported by the EDGE architecture; and d) universal mechanisms for data-parallel architectures.