In this article we have designed an efficient reconfigurable finite impulse response (RFIR) filter for the software defined radio applications. The proposed filter is designed with the sub modules as the adders and multipliers considering the hardware resource utilizations interms of throughput, latency, area, power consumption and delay. The useof parallel prefix adder (PPA) for partial products summation which are produced by multiplier. For faster multiplication, the distributed arithmetic (DA) look up table (LUT) based multiplier is used to multiply the x(n) and h(n) for performing the RFIR filter. The module is tested in both the platform MATLAB and Xilinx FPGA for random audio signal with and without noise. The Xilinx XPower analyzer shows 81mW onchip power required for the selected target Spartan 3E FPGA board. [ABSTRACT FROM AUTHOR]
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